1.6 – Check Tamper Resistance Features

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1.6 – Check Tamper Resistance Features

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Requirement Description

Verify the presence of tamper resistance and/or tamper detection features in the DUT, ensuring the device can detect and/or resist unauthorized attempts to modify or interfere with its hardware or software. This includes mechanisms to:

• Prevent or detect software tampering (e.g., firmware integrity checks, secure boot).

• Prevent or detect hardware tampering (e.g., tamper-evident seals, intrusion detection sensors).

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DUT Software Details

• Software Name/Version: ___________________

• Build Date: ___________________

• Build Number: ___________________

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Hash Checksum Verification for DUT’s Software Image

• Algorithm Used: SHA-256 (or other approved algorithm)

• Expected Hash: ___________________

• Calculated Hash: ___________________

• Result: Pass / Fail

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DUT Configuration

(Insert any commands, settings, or features enabled to verify tamper resistance and detection functionality.) Example:

show security tamper-status
show system integrity

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Pre-Conditions

The vendor shall provide the following:

1. Documentation of measures available in the device to prevent software tampering (e.g., code signing, secure boot, runtime integrity monitoring).

2. Documentation of measures available in the device to prevent hardware tampering (e.g., tamper-evident seals, enclosure sensors, secure enclosures).

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Test Plan

Total Number of Test Cases: 2

Planned Test Cases:

1. BIS-1.6.1 – Verification of software tamper resistance/detection features.

2. BIS-1.6.2 – Verification of hardware tamper resistance/detection features.

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Test-bed Diagram with Interfaces and IPs

(Attach diagram showing DUT, test equipment, tamper detection interface connections, and any monitoring tools used.)

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